1. Field
Various embodiments of the present invention relate to an image sensor and, more particularly, a counting apparatus, an analog-to-digital converter and a complementary metal oxide semiconductor (CMOS) image sensor including the same.
2. Description of the Related Art
An analog-to-digital converter (ADC) of a CMOS image sensor is generally implemented by a column parallel ADC since it is much smaller compared with a conventional ADC. The column parallel ADC includes a digital-to-analog converter (i.e. a ramp signal generator), a plurality of comparators, a plurality of n-bit counters each being coupled to a respective comparator, and a plurality of n-bit memories each being coupled to a respective counter.
Each of the comparators compares a pixel signal (i.e. a pixel voltage) from a pixel connected thereto with a ramp signal that is output by the ramp signal generator and works as a reference voltage to control an operation of a corresponding counter. Thus, the counter is controlled according to an output signal of the comparator and counts a clock signal input thereto. The memory stores and maintains digital data of the pixel signal obtained by the operation of the ADC, so that the counter continues to operate while the digital data is being read out.
In such an operation process, each comparator and each counter operates independently from other comparators and counters. Accordingly, the power consumption in each counter increases with the number of counts. Thus, if the number of counts could be decreased, the power consumption in the counters would be reduced as well.